The present invention relates to a variable delay circuit calibrating method applicable to a timing generator which is used, for example, in an IC tester, and a variable delay circuit which performs calibration by the method.
Conventional IC testers are provided with a timing generator, and use a timing signal available therefrom to define, for example, the timing of the rise and fall of a test signal which is applied to an IC under test.
The IC tester changes little by little the tiring of the rise and fall of the test pattern signal for application to the IC under test to conduct various tests thereon such as measurement of the range of timing over which the IC under test operates normally. To perform this, the timing generator is designed to be capable of finely changing the timing generation.
FIG. 1 is a diagrammatic representation of the basic construction of a variable delay circuit. M delay stages DY.sub.1 to DY.sub.M are connected in cascade through M-1 multiplexers MUX.sub.1 to MUX.sub.M-1, respectively, and the output of the last delay stage DY.sub.M is connected via a multiplexer MUX.sub.M to an output terminal OUT. The amounts of delay of the delay stages DY.sub.1 to DY.sub.M are weighted differently. In this prior art example, an m-th delay stage DY.sub.m is weighted by a series connection of 2.sup.m delay elements DE having about the same amount of delay d. Each delay element DE is formed, for example, by an AND gate, and has an amount of delay of 1 to 2 psec. The delay stages DY.sub.1 to DY.sub.M have their inputs and outputs connected to input terminals A and B of the multiplexers MUX.sub.1 to MUX.sub.M respectively corresponding thereto. The multiplexers MUX.sub.1 to MUX.sub.M select and output either one of signals fed to their input terminals A and B in response to control signals c.sub.1 to c.sub.M applied to their control terminals S. Let it be assumed that each multiplexer selects the input terminal A or output terminal B, depending on whether the control signal c fed to the control terminal S is high- or low-level. Accordingly, when signals to control input terminals T1 to TM are all low-level, the multiplexers MUX.sub.1 to MUX.sub.M all switch to the input terminals B, with the result that the delay time between input and output terminals IN and OUT is minimized. This minimum delay time will hereinafter be referred to as an offset delay time.
If all the delay elements ideally have the same amount of delay d, it is possible with the variable delay circuit of FIG. 1 that the entire amount of delay from the input to output terminals IN and OUT is set at 2.sup.M values which differ by steps of d. In such an instance, the range over which amounts of delay can be set is 0 to d(2.sup.M -1). Then, letting the delay resolution (the minimum delay unit) necessary for setting of timing in the timing generator of the IC tester be represented by d.sub.s =d and the maximum amount of delay by d.sub.s (2.sup.M -1) as depicted in FIG. 2-Row A, desired amounts of delay can be set over the required range in the minimum delay unit which is required by the FIG. 1 construction. The graduations in ds units depicted in FIG. 2-Row A will hereinafter be referred to as nominal delay graduations and their values D.sub.s1, D.sub.s2, D.sub.s3, . . . as nominal delay values.
In practice, however, the amounts of delay d of the delay elements DE vary, and delays by other connection lines than the delay elements are also added. Then, assume that an N-bit delay setting signal CS is used to set nominal amounts of delay. In this instance, as depicted in FIG. 2-Row B, the amount of delay d of each delay element DE is chosen to be sufficiently smaller (for example, less than 1/2) than the nominal delay resolution d.sub.s required for the variable delay circuit, and the value M is determined so that substantially the maximum amount of delay d(2.sup.M -1) becomes larger than the required maximum amount of delay d.sub.s (2.sup.N -1). Then the amounts of delay are measured for all of 2.sup.M -1 set values of an M-bit control signal CC. And the N-bit delay setting signal values CS are predetermined which provide amounts of delay that minimize errors which deviate from the nominal delay values D.sub.s1, D.sub.s2, . . . of the nominal graduations depicted in FIG. 2-Row A.
Since the amounts of delay of the delay elements DE are subject to variation as referred to above, it is necessary to determine the control signal values CC which minimize errors of actual delay times with respect to nominal delay set values 0 psec, 10 psec, 20 psec, 30 psec, . . . . When the delay stages DY.sub.1, DY.sub.2, DY.sub.3, . . . are formed by semiconductor elements, their delay times vary with a temperature change as well.
In view of the above, the conventional IC tester suspends the test at fixed time intervals after its startup, then measures delay times by all combinations of the delay stages DY.sub.1 to DY.sub.M, then based on the measured delay times, selects the optimum combination of delay stages (that is, the control signal values CC) which minimize errors with respect to the set nominal amounts of delay, and performs such a calibration as to make the actual delay times bear as linear a relationship as possible to the nominal amounts of delay.
FIG. 3 shows an example of a conventional variable delay circuit which performs such operations. Reference numeral 11 denotes a converter connected to the control input terminals T.sub.1 to T.sub.M. The nominal delay setting signal CS is converted by the converter 11 to the control signal value CC for selecting an error-minimizing combination of delay stages obtained by measurement. The converted control signal value CC is used to control the multiplexers MUX.sub.1 to MUX.sub.M.
In FIG. 4A there is depicted an example of the results of measurement of the delay times corresponding to the respective values of the control signal CC. Let it be assumed here that the required nominal minimum delay step (resolution) d.sub.s is 10 psec and that the delay time up to 1 nsec can be set in steps of 10 psec nominally. In the measurements the amount of delay of each delay element DE was about 2 psec, and the delay times were measured by controlling the multiplexers MUX.sub.1 to MUX.sub.M with the control signal value CC=(c.sub.1, c.sub.2, c.sub.3, . . . , c.sub.10) of M=10 bits while changing the control signal value CC from 0 to 2.sup.10 -1. It must be noted here that the delay times are reverse in length between columns 7 and 8 of the control signal value CC and between 23 and 24. Conventionally, the measured values of the delay times, when obtained, are immediately sorted (rearranged) in an ascending order as depicted in FIG. 4B. The values of the control signal CC, which provided respective delay times, are also sorted corresponding thereto.
From such rearranged delay times are selected a sequence of delay times arranged nearly at required intervals of, for example, d.sub.s =10 psec, and the values of the control signal CC accompanying the selected delay times are sequentially arranged in a one-to-one correspondence with the nominal delay setting values CS in a calibration table (FIG. 4C). The CS-CC calibration table is stored in the converter 11. That is, when supplied with the nominal delay setting signal CS, the converter 11 converts its value to the control signal CC, which is used to control the multiplexers MUX.sub.1 to MUX.sub.M to provide a delay time closest to the ideal value at that point in time.
As described above, the prior art employs the method of obtaining the control signal value CC by measuring the delay times of the delay stages DY.sub.1 to DY.sub.M, rearranging the measured delay times through sorting, and selecting from the rearranged delay times a sequence of delay times which switch at predetermined intervals. Hence, the conventional method is time-consuming.
That is, since the actual IC tester is provided with a large umber (1500 to 2000) of such variable delay circuits 100 as depicted in FIG. 3, much time is needed to calibrate the delay time of each variable delay circuit. Additionally, the prior art adopts the method of obtaining the control signal value CC while storing the arrangement of the measured delay times, the arrangement of the sorted delay times and the arrangement of the delay times selected from the sorted delay times; hence, simultaneous calibration of delay times of, for example, about 100 variable delay circuits inevitably occupies an enormously wide storage area of a memory.